The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 2016
Filed:
May. 27, 2015
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Jin-wook Jang, Asan-si, KR;
Se-jin Yoo, Asan-si, KR;
Sung-il Cho, Asan-si, KR;
Jae-ho Choi, Cheonan-si, KR;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/31 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 24/09 (2013.01); H01L 23/3135 (2013.01); H01L 23/3142 (2013.01); H01L 23/481 (2013.01); H01L 23/49838 (2013.01); H01L 24/17 (2013.01); H01L 25/0657 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16227 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01);
Abstract
A semiconductor package includes a wiring substrate including a plurality of solder pads; a chip including a plurality of chip pads connected to the solder pads through a plurality of solders; a sealing layer configured to seal the chip and the solders, at least one void being between the solders; and a solder extrusion prevention layer on one sidewall of the solder exposed by the at least one void.