IDiyas

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9412589 B1

PDFFull Text
Date of Patent:
Aug. 09, 2016

Filed:

Sep. 30, 2014

Method for fabricating nmos and pmos transistors on a substrate of the soi, in particular fdsoi, type and corresponding integrated circuit

Applicant:

Stmicroelectronics (Crolles 2) Sas, Crolles, FR;

Inventors:

David Barge, Grenoble, FR;

Philippe Garnier, Meylan, FR;

Yves Campidelli, Le Moutaret, FR;

Assignee:

STMICROELECTRONICS (CROLLES 2) SAS, Crolles, FR;

Attorney:

Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.

Primary Examiner:

Earl Taylor

Int. Cl.
CPC ...
H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 21/02 (2006.01); H01L 27/12 (2006.01); H01L 21/84 (2006.01); H01L 29/417 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/786 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02609 (2013.01); H01L 21/0262 (2013.01); H01L 21/02532 (2013.01); H01L 21/02576 (2013.01); H01L 21/02579 (2013.01); H01L 21/02636 (2013.01); H01L 21/84 (2013.01); H01L 27/1203 (2013.01); H01L 29/41733 (2013.01); H01L 29/42384 (2013.01); H01L 29/66742 (2013.01); H01L 29/78618 (2013.01);
Abstract

An integrated circuit includes an NMOS transistor and a PMOS transistor on different regions of an SOI substrate. Each transistor includes a gate region, multilayer lateral insulating regions against the sides of the gate region while also on the substrate. Each multilayer lateral insulating region includes an inclined portion sloping away from the substrate. Source and drain regions are on the substrate and are separated from the sides of the gate region by the corresponding multilayer lateral insulating region. The source and drain regions have an inclined portion resting against the inclined portion of the the lateral insulating region.

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