The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2016

Filed:

Sep. 03, 2015
Applicants:

Commissariat À{grave Over ( )}l'énergie Atomique ET Aux Énergies Alternatives, Paris, FR;

Centre National DE LA Recherche Scientifique, Paris, FR;

Inventors:

Grégory Di Pendina, Echirolles, FR;

Edith Beigne, Meaudre, FR;

Eldar Zianbetov, Echirolles, FR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 14/00 (2006.01); G11C 13/00 (2006.01); G11C 11/14 (2006.01); H03K 19/017 (2006.01); H03K 19/0185 (2006.01); H03K 19/20 (2006.01); G11C 11/16 (2006.01); G11C 11/22 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G11C 11/14 (2013.01); G11C 11/1675 (2013.01); G11C 11/22 (2013.01); G11C 11/2275 (2013.01); G11C 13/0004 (2013.01); H03K 19/01707 (2013.01); H03K 19/018585 (2013.01); H03K 19/20 (2013.01);
Abstract

The invention concerns a circuit comprising: a C-element having first and second input nodes and first and second inverters () cross-coupled between first and second complementary storage nodes (, Z), the second storage node (Z) forming an output node of the C-element; and a non-volatile memory comprising: a first resistive element () having a first terminal coupled to the first storage node (); a second resistive element () having a first terminal coupled to the second storage node (Z), at least one of the first and second resistive elements being programmable to have one of at least two resistive states (R, R), wherein a second terminal of the first resistive element () is coupled to a second terminal of the second resistive element () via a first transistor (); and a control circuit ().


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