The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 09, 2016

Filed:

Aug. 30, 2011
Applicants:

Ninghui Sun, Beijing, CN;

Fei Chen, Beijing, CN;

Zheng Cao, Beijing, CN;

Kai Wang, Beijing, CN;

Xuejun an, Beijing, CN;

Inventors:

Ninghui Sun, Beijing, CN;

Fei Chen, Beijing, CN;

Zheng Cao, Beijing, CN;

Kai Wang, Beijing, CN;

Xuejun An, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/173 (2006.01); G06F 15/76 (2006.01); G06F 9/52 (2006.01); G06F 9/30 (2006.01);
U.S. Cl.
CPC ...
G06F 15/76 (2013.01); G06F 9/3004 (2013.01); G06F 9/30087 (2013.01); G06F 9/52 (2013.01);
Abstract

The invention discloses a multiprocessor System and synchronous engine device thereof. the synchronous engine includes: a plurality of storage queues, wherein one of the queues stores all synchronization primitives from one of the processors; a plurality of scheduling modules, selecting the synchronization primitives for execution from the plurality of storage queues and then according to the type of the synchronization primitive transmitting the selected synchronization primitives to corresponding processing modules for processing, scheduling modules corresponding in a one-to-one relationship with the storage queues; a plurality of processing modules, receiving the transmitted synchronization primitives to execute different functions; a virtual synchronous memory structure module, using small memory space and mapping main memory spaces of all processors into a synchronization memory structure to realize the function of all synchronization primitives through a control logic; a main memory port, communicating with virtual synchronous memory structure module to read and write the main memory of all processors, and initiate an interrupt request to processors; a configuration register, storing various configuration information required by processing modules.


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