The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 09, 2016
Filed:
Jun. 22, 2009
Avinash Jindal, Milpitas, CA (US);
Deepak Bansal, San Jose, CA (US);
Sam Htin Moy, Daly City, CA (US);
David Cheung, Cupertino, CA (US);
Bing Wang, San Jose, CA (US);
Mani Kancherla, Milpitas, CA (US);
Sridhar Devarapalli, Santa Clara, CA (US);
Avinash Jindal, Milpitas, CA (US);
Deepak Bansal, San Jose, CA (US);
Sam Htin Moy, Daly City, CA (US);
David Cheung, Cupertino, CA (US);
Bing Wang, San Jose, CA (US);
Mani Kancherla, Milpitas, CA (US);
Sridhar Devarapalli, Santa Clara, CA (US);
Brocade Communications Systems, Inc., San Jose, CA (US);
Abstract
A network device includes a plurality of blades, each having a plurality of CPU cores that process requests received by the network device. Each blade further includes an accumulator circuit. Each accumulator circuit periodically aggregates the local counter values of the CPU cores of the corresponding blade. One accumulator circuit is designated as a master, and the other accumulator circuit(s) are designated as slave(s). The slave accumulator circuits transmit their aggregated local counter values to the master accumulator circuit. The master accumulator circuit aggregates the sets of aggregated local counter values to create a set of global counter values. The master accumulator circuit transmits the global counter values to a management processor (for display), to the CPU cores located on its corresponding blade, and to each of the slave accumulator circuits. Each slave accumulator circuit then transmits the global counter values to the CPU cores located on its corresponding blade.