The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2016

Filed:

Mar. 05, 2013
Applicant:

Kyocera Corporation, Kyoto-shi, Kyoto, JP;

Inventors:

Mahiro Tsujino, Kyoto, JP;

Eiichi Katayama, Kyoto, JP;

Emi Mukai, Kyoto, JP;

Atsushi Ogasawara, Kyoto, JP;

Assignee:

Kyocera Corporation, Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 5/00 (2006.01); H05K 1/18 (2006.01); H01L 23/057 (2006.01); H05K 1/16 (2006.01);
U.S. Cl.
CPC ...
H05K 1/181 (2013.01); H01L 23/057 (2013.01); H05K 1/162 (2013.01); H05K 1/167 (2013.01); H05K 1/184 (2013.01); H05K 1/189 (2013.01); H01L 2924/0002 (2013.01); H05K 2201/0344 (2013.01); H05K 2201/10075 (2013.01); H05K 2201/10083 (2013.01); H05K 2201/10143 (2013.01); H05K 2201/10166 (2013.01); H05K 2201/10174 (2013.01); H05K 2201/10196 (2013.01);
Abstract

A device housing package includes a substrate in a form of a rectangle, having a mounting region of a device at an upper surface thereof; a frame body disposed on the substrate so as to extend along an outer periphery of the mounting region, the frame body having a cutout formed at a part thereof; and an input-output terminal disposed in the cutout. The input-output terminal includes a first insulating layer, a second insulating layer overlaid on the first insulating layer, and a third insulating layer overlaid on the second insulating layer. First terminals set at a predetermined potential are disposed on an upper surface of the first insulating layer. Second terminals set at a predetermined potential are disposed on a lower surface of the first insulating layer. Third terminals through which AC signals flow are disposed on an upper surface of the second insulating layer.


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