The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2016

Filed:

Jan. 15, 2014
Applicant:

Honeywell International Inc., Morristown, NJ (US);

Inventors:

Nan Wang, Shang Hai, CN;

Orville Nyhus, Glendale, AZ (US);

Chao Wang, Shanghai, CN;

Assignee:

Honeywell International Inc., Morris Plains, NJ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/14 (2006.01); H01Q 21/00 (2006.01); H05K 1/02 (2006.01); H05K 1/11 (2006.01); H05K 3/46 (2006.01); H05K 3/10 (2006.01); H01Q 1/00 (2006.01); H01P 3/08 (2006.01); H01Q 1/24 (2006.01); H01Q 1/50 (2006.01);
U.S. Cl.
CPC ...
H05K 1/144 (2013.01); H01P 3/084 (2013.01); H01Q 1/002 (2013.01); H01Q 21/0081 (2013.01); H05K 1/0251 (2013.01); H05K 1/0298 (2013.01); H05K 1/115 (2013.01); H05K 1/14 (2013.01); H05K 3/10 (2013.01); H05K 3/46 (2013.01); H01L 2224/00 (2013.01); H01Q 1/246 (2013.01); H01Q 1/50 (2013.01); H05K 2201/10007 (2013.01); Y10T 29/49126 (2015.01); Y10T 29/49155 (2015.01);
Abstract

Systems and methods for a feeding structure for an antenna array are provided. In at least one embodiment, the feeding structure for an antenna array comprises one or more circuit boards with one or more circuits formed thereon, one or more conductive layers wherein the one or more circuit boards are mounted to the one or more conductive layers, and one or more connectors coupled to the one or more circuits through an opening in the one or more conductive layers. Furthermore, the one or more conductive layers are separated by a dielectric from the one or more circuits and the one or more conductive layers contact the one or more circuit boards such that the one or more circuits are isolated from the one or more conductive layers.


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