The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2016

Filed:

Feb. 15, 2016
Applicant:

Mediatek Inc., Hsin-Chu, TW;

Inventors:

Saravanan Rajapandian, Austin, TX (US);

Caiyi Wang, Austin, TX (US);

Jing Li, Austin, TX (US);

Ravikanth Suravarapu, Austin, TX (US);

Narayanan Baskaran, Austin, TX (US);

Assignee:

MEDIATEK INC., Hsin-Chu, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04B 7/00 (2006.01); H04B 1/40 (2015.01); H04B 1/00 (2006.01); H04L 5/12 (2006.01); H04W 88/12 (2009.01); H03G 3/30 (2006.01);
U.S. Cl.
CPC ...
H04B 1/005 (2013.01); H03G 3/3036 (2013.01);
Abstract

A current buffer used in a receiver arrangement includes a direct path mode and a mirror path mode. The direct path mode includes a plurality of first set of transistors and a plurality of first set of current sources turned on while all remaining transistors and current sources are turned off, during the direct path mode a current signal at an input node directly appears at an output node. The mirror path mode includes a first transistor and a first current source being turned off while a plurality of second set of transistors and a plurality of second set of current sources are turned on. The current signal goes through a current mirror pair and appears at the output node with a gain which is controlled by slicing one of transistors of the current mirror pair and a second current source allowing multiple gains in the mirror path mode.


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