The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2016

Filed:

Jun. 27, 2014
Applicant:

Finisar Corporation, Sunnyvale, CA (US);

Inventors:

Arik Zafrany, Santa Clara, CA (US);

Georgios Kalogerakis, Mountain View, CA (US);

Assignee:

FINISAR CORPORATION, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03B 1/00 (2006.01); H03K 3/00 (2006.01); H03K 17/687 (2006.01); H03F 3/45 (2006.01); H01S 5/042 (2006.01); H04B 10/50 (2013.01);
U.S. Cl.
CPC ...
H03K 17/6871 (2013.01); H01S 5/0427 (2013.01); H03F 3/45085 (2013.01); H03F 3/45179 (2013.01); H03F 3/45282 (2013.01); H01S 5/042 (2013.01); H03F 2203/45301 (2013.01); H03F 2203/45554 (2013.01); H03F 2203/45562 (2013.01); H03F 2203/45598 (2013.01); H03F 2203/45702 (2013.01); H04B 10/502 (2013.01);
Abstract

A circuit may include first and second input nodes, first and second output nodes, first and second intermediate nodes, first and second resistances, a first amplification transistor coupled to the first input node, the first resistance, and the first intermediate node and a second amplification transistor coupled to the second input node, the second resistance, and the second intermediate node. The circuit may also include a first active device coupled to the first output node and the first intermediate node, a second active device coupled to the second output node and the second intermediate node, a first output transistor coupled to the first output node and configured to conduct based on a second intermediate signal on the second intermediate node, and a second output transistor coupled to the second output node and configured to conduct based on a first intermediate signal on the first intermediate node.


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