The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2016

Filed:

Jan. 08, 2010
Applicants:

Munehiro Tada, Tokyo, JP;

Toshitsugu Sakamoto, Tokyo, JP;

Hiromitsu Hada, Tokyo, JP;

Naoki Banno, Tokyo, JP;

Inventors:

Munehiro Tada, Tokyo, JP;

Toshitsugu Sakamoto, Tokyo, JP;

Hiromitsu Hada, Tokyo, JP;

Naoki Banno, Tokyo, JP;

Assignee:

NEC CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01); H01L 27/22 (2006.01); H01L 27/24 (2006.01); H01L 27/10 (2006.01);
U.S. Cl.
CPC ...
H01L 45/085 (2013.01); H01L 27/228 (2013.01); H01L 27/2436 (2013.01); H01L 45/04 (2013.01); H01L 45/1233 (2013.01); H01L 45/146 (2013.01); H01L 45/1625 (2013.01); H01L 45/1675 (2013.01); H01L 27/101 (2013.01);
Abstract

A semiconductor device comprises a semiconductor substrate; a multilevel wiring layer structure on the semiconductor substrate; and a variable resistance element in the multilevel wiring layer structure, wherein the variable resistance element comprises a variable resistance element film whose resistance changes between a top electrode and a bottom electrode, wherein the multilevel wiring layer structure comprises at least a wiring electrically connected to the bottom electrode and a plug electrically connected to the top electrode, and wherein the wiring also serves as the bottom electrode.


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