The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2016

Filed:

Apr. 21, 2015
Applicant:

Powerchip Technology Corporation, Hsinchu, TW;

Inventors:

Chun-Yu Chuang, Taoyuan, TW;

Yi-Lin Hsu, Hsinchu County, TW;

Liang-Chuan Lai, Hsinchu County, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 21/283 (2006.01); H01L 21/762 (2006.01); H01L 27/115 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66825 (2013.01); H01L 21/283 (2013.01); H01L 21/28273 (2013.01); H01L 21/76224 (2013.01); H01L 27/11524 (2013.01); H01L 29/66553 (2013.01);
Abstract

A method of manufacturing an isolation structure suitable for a non-volatile memory is provided. A substrate is provided. A dielectric layer, a conductive layer, and a hard mask layer are sequentially formed on the substrate. The hard mask layer and the conductive layer are patterned to form a first trench which exposes the dielectric layer. A first liner is formed on the substrate. The first liner and the dielectric layer that are exposed by the first trench are removed to expose the substrate. A spacer is formed on sidewalls of the conductive layer and the hard mask layer. The substrate is partly removed to form in a second trench with use of the conductive layer and the hard mask layer with the spacer as a mask. An isolation layer is formed in the second trench. The distance between the conductive layers is greater than the width of the second trench.


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