The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 02, 2016
Filed:
Mar. 25, 2015
Applicant:
Samsung Electronics Co., Ltd., Suwon-si, KR;
Inventors:
Hyun-Seung Song, Incheon, KR;
Hwi-Chan Jun, Yongin-si, KR;
Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 29/45 (2006.01); H01L 21/285 (2006.01); H01L 49/02 (2006.01); H01L 29/66 (2006.01); H01L 27/06 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/456 (2013.01); H01L 21/28518 (2013.01); H01L 21/28568 (2013.01); H01L 27/0629 (2013.01); H01L 28/24 (2013.01); H01L 29/66545 (2013.01); H01L 29/513 (2013.01); H01L 29/517 (2013.01); H01L 29/665 (2013.01);
Abstract
Provided is a method of fabricating a semiconductor device. The method includes providing a substrate including a transistor area and a resistor area, forming dummy gate structures on the substrate in the resistor area, and a lower interlayer insulating layer; forming a resistor structure having a buffer insulating pattern, a resistor element and an etch-retard pattern disposed sequentially on the lower interlayer insulating layer; and forming resistor contact structures configured to pass through the etch-retard pattern and to contact with the resistor element.