The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2016

Filed:

Jun. 17, 2014
Applicant:

Robert Bosch Gmbh, Stuttgart, DE;

Inventors:

Heribert Weber, Nuertingen, DE;

Hartmut Kueppers, Reutlingen, DE;

Jens Frey, Filderstadt, DE;

Neil Davies, Sonnenbuehl-Genkingen, DE;

Jochen Reinmuth, Reutlingen, DE;

Assignee:

ROBERT BOSCH GMBH, Stuttgart, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 29/06 (2006.01); H01L 25/065 (2006.01); H01L 23/31 (2006.01); B81C 1/00 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0657 (2013.01); B81C 1/00238 (2013.01); H01L 23/3114 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); B81C 2203/0118 (2013.01); B81C 2203/0792 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48471 (2013.01); H01L 2225/06506 (2013.01); H01L 2225/06568 (2013.01);
Abstract

A vertically integrated hybrid component is implemented in the form of a wafer level package including: at least two element substrates assembled one above the other; a molded upper sealing layer made of an electrically insulating casting; and an external electrical contacting of the component being implemented on the top side via at least one contact stamp which is embedded in the sealing layer so that (i) its lower end is connected to a wiring level of an element substrate and (ii) its upper end is exposed in the surface of the sealing layer.


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