The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2016

Filed:

Apr. 20, 2015
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventor:

Qun Shao, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/302 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01); H01L 29/49 (2006.01); H01L 21/8238 (2006.01); H01L 21/02 (2006.01); H01L 21/3105 (2006.01); H01L 21/32 (2006.01); H01L 21/3213 (2006.01); H01L 21/321 (2006.01); H01L 21/311 (2006.01); H01L 21/033 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 21/02164 (2013.01); H01L 21/02238 (2013.01); H01L 21/0332 (2013.01); H01L 21/31053 (2013.01); H01L 21/31116 (2013.01); H01L 21/32 (2013.01); H01L 21/3212 (2013.01); H01L 21/32135 (2013.01); H01L 21/823828 (2013.01); H01L 29/495 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method for fabricating a semiconductor device includes providing a semiconductor substrate having a first region and a second region; and forming at least one first dummy gate in the first region and at least one second dummy gate in the second region. Further, the method includes forming a dielectric layer with a top surface leveling with a surface of the first dummy gate on the semiconductor substrate; oxidizing a top portion of the second dummy gate to form a protective layer to prevent over-polishing on the second region; removing the first dummy gate to form a first gate trench; forming a first metal layer to fill the first gate trench and cover the protective layer and the dielectric layer; and removing a portion of the first metal layer higher than the dielectric layer to form a first metal gate in the first gate trench.


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