The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2016

Filed:

Oct. 02, 2014
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Jae-Hoon Lee, Suwon-si, KR;

Tae-Geun Kim, Bucheon-si, KR;

Chan-Ho Park, Seongnam-si, KR;

Hyun-Jung Her, Hwaseong-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/739 (2006.01); H01L 21/761 (2006.01); H01L 21/265 (2006.01); H01L 29/40 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 21/761 (2013.01); H01L 21/265 (2013.01); H01L 29/0619 (2013.01); H01L 29/0834 (2013.01); H01L 29/402 (2013.01); H01L 29/66348 (2013.01); H01L 29/7397 (2013.01);
Abstract

A semiconductor power device includes a substrate, a plurality of gate electrode structures, a floating well region and a termination ring region. The substrate has a first region and a second region. A plurality of gate electrode structures is formed on the substrate, each of the gate electrode structures extends from the first region to the second region and includes a first gate electrode, a second gate electrode and a connecting portion, the first and second gate electrodes extend in a first direction, and the connecting portion connects end portions of the first and second gate electrodes to each other. The floating well region is doped with impurities between the gate electrode structures in the first region of the substrate, and the floating well region has a first impurity concentration and a first depth. The termination ring region is doped with impurities in the second region of the substrate, is spaced apart from the gate electrode structures, and has a ring shape surrounding the first region, and has the first impurity concentration and the first depth. The semiconductor power device may have a high breakdown voltage.


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