The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2016

Filed:

Mar. 27, 2014
Applicant:

Oracle International Corporation, Redwood City, CA (US);

Inventors:

Jee Ho Ryoo, Austin, TX (US);

Karthik Ganesan, Austin, TX (US);

Yao-Min Chen, San Jose, CA (US);

Assignee:

Oracle International Corporation, Redwood Shores, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G11C 8/06 (2006.01); G11C 5/04 (2006.01); G11C 8/12 (2006.01);
U.S. Cl.
CPC ...
G11C 8/06 (2013.01); G11C 5/04 (2013.01); G11C 8/12 (2013.01);
Abstract

A memory subsystem incorporating a die-stacked DRAM (DSDRAM) is disclosed. In one embodiment, a system include a processor implemented on a silicon interposer of an integrated circuit (IC) package, a DSDRAM coupled to the processor, the DSDRAM implemented on the silicon interposer of the IC package, and a DRAM implemented separately from the IC package. The DSDRAM and the DRAM form a main memory having a contiguous address space comprising a range of physical addresses. The physical addresses of the DSDRAM occupy a first contiguous portion of the address space, while the DRAM occupies a second contiguous portion of the address space. Each physical address of the contiguous address space is augmented with a first bit that, when set, indicates that a page is stored in the DRAM and the DSDRAM.


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