The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 02, 2016
Filed:
Dec. 05, 2014
Xilinx, Inc., San Jose, CA (US);
Nagaraj Savithri, Plano, TX (US);
Vinod K. Nakkala, Hyderabad, IN;
Atul Srinivasan, Woodside, CA (US);
Sudip K. Nag, San Jose, CA (US);
XILINX, INC., San Jose, CA (US);
Abstract
Determining delays of paths in a circuit design includes determining whether or not each path of the plurality of paths matches a path definition of a plurality of path definitions in a path database. For each path that matches a path definition, a first path delay value associated with the matching path definition is read from the path database and associated with the matching path of the circuit design. For each path that does not match any of the path definitions, respective element delay values of elements of the path are read from an element database. A second path delay value of the non-matching path is computed as a function of the respective element delay values, and the second path delay value is associated with the path. The first and second path delay values are output along with information indicating the associated paths.