The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2016

Filed:

Jun. 06, 2014
Applicant:

Super Talent Technology, Corp., San Jose, CA (US);

Inventors:

Frank Yu, Palo Alto, CA (US);

Abraham C. Ma, Fremont, CA (US);

Shimon Chen, Los Gatos, CA (US);

Assignee:

Super Talent Technology, Corp., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 13/00 (2006.01); G06F 13/28 (2006.01); G06F 11/10 (2006.01); G06F 3/06 (2006.01); G11C 29/00 (2006.01); G06F 12/02 (2006.01); G11C 11/56 (2006.01); G06F 12/08 (2016.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1072 (2013.01); G06F 3/0616 (2013.01); G06F 3/0619 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 3/0685 (2013.01); G06F 12/0246 (2013.01); G06F 12/0871 (2013.01); G11C 11/56 (2013.01); G11C 29/72 (2013.01); G06F 12/0804 (2013.01); G06F 2212/401 (2013.01); G06F 2212/402 (2013.01); G06F 2212/7203 (2013.01); G06F 2212/7208 (2013.01); G11C 13/0004 (2013.01); G11C 29/765 (2013.01); G11C 2211/5641 (2013.01);
Abstract

A controller for a Super Enhanced Endurance Device (SEED) or Solid-State Drive (SSD) increases flash endurance using a DRAM buffer. Host accesses to flash are intercepted by the controller and categorized as data types of paging files, temporary files, meta-data, and user data files, using address ranges and file extensions read from meta-data tables. Paging files and temporary files are optionally written to flash. Full-page and partial-page data are grouped into multi-page meta-pages by data type in the DRAM before storage by lower-level flash devices such as eMMC, UFS, or iSSD. Caches in the DRAM buffer for storing each data type are managed and flushed to the flash devices by the controller. Write dates are stored for pages or blocks for management functions. A spare/swap area in DRAM reduces flash wear. Reference voltages are adjusted when error correction fails.


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