The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 02, 2016

Filed:

Feb. 25, 2015
Applicant:

Elmos Semiconductor Ag, Dortmund, DE;

Inventor:

Michael Doelle, Dortmund, DE;

Assignee:

ELMOS Semiconductor AG, Dortmund, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B81B 7/02 (2006.01); B81C 1/00 (2006.01); G01L 9/00 (2006.01); B81B 3/00 (2006.01); H01L 29/49 (2006.01); H01L 29/84 (2006.01);
U.S. Cl.
CPC ...
B81C 1/00158 (2013.01); B81B 3/007 (2013.01); B81B 3/0018 (2013.01); B81B 3/0021 (2013.01); B81B 3/0072 (2013.01); B81B 3/0081 (2013.01); B81C 1/00626 (2013.01); G01L 9/0047 (2013.01); H01L 29/4916 (2013.01); B81B 2201/0235 (2013.01); B81B 2201/0264 (2013.01); B81B 2203/0127 (2013.01); B81C 2201/019 (2013.01); H01L 29/84 (2013.01);
Abstract

The micro-electromechanical semiconductor component is provided with a semiconductor substrate (), a reversibly deformable bending element () made of semiconductor material, and at least one transistor that is sensitive to mechanical stresses, said transistor being designed as an integrated component in the bending element (). The transistor is arranged in an implanted active region pan () that is made of a semiconductor material of a first conducting type and is introduced in the bending element (). Two mutually spaced, implanted drain and source regions () made of a semiconductor material of a second conducting type are designed in the active region pan (), a channel region extending between said two regions. Implanted feed lines made of a semiconductor material of the second conducting type lead to the drain and source regions (). The upper face of the active region pan () is covered by a gate oxide (). In the area of the channel region, a gate electrode () made of polysilicon is located on the gate oxide (), a feed line likewise made of polysilicon leading to said gate electrode.


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