The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2016

Filed:

Jun. 25, 2015
Applicant:

Kyocera Circuit Solutions, Inc., Kyoto, JP;

Inventors:

Shinri Saeki, Shimoniikawa-gun, JP;

Takashi Ishioka, Namerikawa, JP;

Satoshi Nakamura, Kurobe, JP;

Assignee:

Kyocera Corporation, Kyoto-Shi, Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/02 (2006.01); H05K 3/18 (2006.01); C25D 5/02 (2006.01); H05K 1/11 (2006.01);
U.S. Cl.
CPC ...
H05K 1/0298 (2013.01); C25D 5/022 (2013.01); H05K 1/115 (2013.01); H05K 3/188 (2013.01);
Abstract

The printed wiring board includes: an insulating board including a conductive metal layer formed on both surfaces of an insulating resin; and a conductor layer formed on both surfaces of the insulating board, the conductor layer including a different circuit pattern depending on a region. The circuit patterns formed on both surfaces of the insulating board includes a pattern with line width accuracy of ±10 μm or less, and a conductor layer thickness in a region having a dense circuit pattern area and a conductor layer thickness in a region having a sparse circuit pattern area have a following relational expression:conductor layer thickness in a dense region/conductor layer thickness in a sparse region=0.7 to 1.0.


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