The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2016

Filed:

Apr. 11, 2014
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Aswin Srinivasa Rao, Dallas, TX (US);

Anand Kudari, Bangalore, IN;

Karthik Subburaj, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03C 1/00 (2006.01); H03K 7/06 (2006.01); H04L 27/12 (2006.01); H04L 27/10 (2006.01);
U.S. Cl.
CPC ...
H03K 7/06 (2013.01); H04L 27/10 (2013.01); H04L 27/12 (2013.01); H04L 27/127 (2013.01);
Abstract

Binary frequency shift keying modulation is implemented by choosing appropriate phases of a high frequency clock to generate a modulated intermediate clock frequency. The high frequency clock is chosen to be (M+0.5)*fc, where fc is the carrier frequency and M is an integer. Depending on the binary data '1' or '0' to be transmitted, ‘M’ or ‘M+1’ clock phases from the high frequency clock are converted to an intermediate clock that is 2*N times faster than the carrier frequency, where N is an integer. This intermediate clock, generated entirely in the digital domain, has the required data modulation in it, and is used to generate N pulse width modulated (PWM) phases of waveforms operating at the carrier frequency. The N phases are then weighed appropriately to synthesize a sine waveform whose lower harmonics are substantially suppressed.


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