The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 26, 2016
Filed:
Sep. 30, 2014
Applicant:
Wafertech, Llc, Camas, WA (US);
Inventor:
Swen Wang, Camas, WA (US);
Assignee:
WAFERTECH, LLC, Camas, WA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 27/115 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 29/167 (2006.01); H01L 21/265 (2006.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 21/26513 (2013.01); H01L 21/28273 (2013.01); H01L 21/768 (2013.01); H01L 29/0642 (2013.01); H01L 29/0847 (2013.01); H01L 29/1095 (2013.01); H01L 29/167 (2013.01);
Abstract
An array of floating gate transistors of a non-volatile memory, NVM, cell includes floating gate transistors separated from one another by high-concentration dopant impurity regions and without using shallow trench isolation (STI) or field oxide (FOX) isolation structures. The array is formed over a substrate portion that includes a continuous and planar upper surface. The high-concentration dopant impurity regions are formed in a P-field region and are formed of the same dopant impurity species as the P-field region but of a higher concentration. The floating gate transistors are split-gate floating gate transistors in some embodiments.