The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2016

Filed:

Dec. 03, 2014
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventor:

Manoj Mehrotra, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/11 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 21/265 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01); H01L 21/266 (2006.01); H01L 21/308 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1104 (2013.01); H01L 21/26513 (2013.01); H01L 21/823807 (2013.01); H01L 21/823814 (2013.01); H01L 21/823864 (2013.01); H01L 27/0922 (2013.01); H01L 27/1116 (2013.01); H01L 29/165 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 29/66636 (2013.01); H01L 29/7834 (2013.01); H01L 29/7848 (2013.01); H01L 21/266 (2013.01); H01L 21/3086 (2013.01);
Abstract

A process of forming an integrated circuit containing a first transistor and a second transistor of the same polarity, by forming an epitaxial spacer layer over gates of both transistors, performing an epitaxial spacer anisotropic etch process to form epitaxial spacers on vertical surfaces adjacent to the first transistor gate and removing the epitaxial spacer layer from the second transistor gate, subsequently performing a source/drain etch process and a source/drain epitaxial process to form source/drain epitaxial regions in the substrate adjacent to the first and second gates, such that the first source/drain epitaxial regions are separated from the first gate by a lateral space which is at least 2 nanometers larger than a second lateral space separating the second source/drain epitaxial regions from the second gate. An integrated circuit formed by the recited process.


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