The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2016

Filed:

Feb. 25, 2015
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Achim Gratz, Dresden, DE;

Scott David Wallace, Moritzburg, DE;

Tobias Jacobs, Dresden, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 23/31 (2006.01); H01L 23/58 (2006.01); H01L 21/78 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 24/94 (2013.01); H01L 21/768 (2013.01); H01L 21/78 (2013.01); H01L 23/3192 (2013.01); H01L 23/5226 (2013.01); H01L 23/53228 (2013.01); H01L 23/562 (2013.01); H01L 23/585 (2013.01); H01L 24/00 (2013.01); H01L 24/03 (2013.01); H01L 22/34 (2013.01); H01L 24/05 (2013.01); H01L 2224/0382 (2013.01); H01L 2224/0392 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/05548 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/1306 (2013.01);
Abstract

A method of processing a semiconductor wafer includes forming semiconductor dies in the semiconductor wafer, each die having an active region containing devices of an integrated circuit and an edge region surrounding the active region, adjacent ones of the dies being separated by a scribe line. The method further includes forming interconnect wiring over the active region of each semiconductor die in an interlayer dielectric, forming ancillary wiring over the edge region of each die in the interlayer dielectric, forming a passivation on the interlayer dielectric, forming bond pads over the interconnect wiring of each die, the bond pads of each die being in electrical connection with the interconnect wiring of that die, and forming additional bond pads over the ancillary wiring of each semiconductor die, the additional bond pads of each die being in electrical connection with the interconnect wiring of that die.


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