The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 26, 2016
Filed:
Sep. 11, 2013
Applicant:
Kabushiki Kaisha Toshiba, Minato-ku, JP;
Inventors:
Masaru Koyanagi, Tokyo, JP;
Yasuhiro Suematsu, Kanagawa, JP;
Assignee:
Kabushiki Kaisha Toshiba, Minato-ku, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/485 (2006.01); H01L 23/522 (2006.01); H01L 25/10 (2006.01); H01L 27/02 (2006.01); H01L 27/06 (2006.01); H01L 25/065 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5228 (2013.01); H01L 25/10 (2013.01); H01L 27/0207 (2013.01); H01L 27/0629 (2013.01); H01L 25/0657 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48145 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/73215 (2013.01); H01L 2224/73265 (2013.01); H01L 2225/06562 (2013.01); H01L 2924/01013 (2013.01); H01L 2924/01074 (2013.01); H01L 2924/15311 (2013.01);
Abstract
According to one embodiment, a semiconductor device includes a transistor formed on a semiconductor chip, a lower-layer wiring connected to a diffusion layer of the transistor, and drawn outside the diffusion layer, and an upper-layer wiring drawn out from a pad electrode formed on the semiconductor chip, connected to the lower-layer wiring, and having resistivity lower than that of the lower-layer wiring.