The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2016

Filed:

Feb. 25, 2013
Applicant:

Shin-etsu Chemical Co., Ltd., Tokyo, JP;

Inventors:

Toshio Shiobara, Annaka, JP;

Susumu Sekiguchi, Takasaki, JP;

Hideki Akiba, Annaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/56 (2006.01); H01L 23/29 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 21/565 (2013.01); H01L 21/561 (2013.01); H01L 23/293 (2013.01); H01L 24/97 (2013.01); H01L 23/3128 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/97 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15787 (2013.01); H01L 2924/181 (2013.01);
Abstract

A method for producing a semiconductor apparatus with a mold including an upper mold half and a lower mold half, includes: an arranging step of arranging on one of the upper mold half and the lower mold half of the mold a substrate on which a semiconductor device is mounted, the mold being kept at a room temperature or heated to a temperature up to 200° C., and arranging on the other of the upper mold half and the lower mold half a substrate on which no semiconductor device is mounted; an integrating step of integrating the substrate on which the semiconductor device is mounted and the substrate on which no semiconductor device is mounted by molding a thermosetting resin with the mold on which the substrates are arranged; and a step of dicing the integrated substrates taken out of the mold to obtain an individualized semiconductor apparatus.


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