The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2016

Filed:

May. 09, 2014
Applicant:

Oracle International Corporation, Redwood City, CA (US);

Inventors:

Thomas A Ziaja, Austin, TX (US);

Murali M. R. Gala, San Jose, CA (US);

Assignee:

Oracle International Corporation, Redwood Shores, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 29/32 (2006.01); G11C 29/12 (2006.01); G11C 7/10 (2006.01); G01R 31/3177 (2006.01); G01R 31/3185 (2006.01); G01R 31/3187 (2006.01); G01R 31/317 (2006.01); G11C 7/22 (2006.01); G06F 11/27 (2006.01);
U.S. Cl.
CPC ...
G11C 29/32 (2013.01); G11C 7/1036 (2013.01); G11C 7/1078 (2013.01); G11C 29/12 (2013.01); G01R 31/3177 (2013.01); G01R 31/3187 (2013.01); G01R 31/31725 (2013.01); G01R 31/31727 (2013.01); G01R 31/318536 (2013.01); G01R 31/318541 (2013.01); G01R 31/318544 (2013.01); G01R 31/318547 (2013.01); G01R 31/318555 (2013.01); G01R 31/318558 (2013.01); G01R 31/318566 (2013.01); G01R 31/318572 (2013.01); G06F 11/27 (2013.01); G11C 7/106 (2013.01); G11C 7/22 (2013.01); G11C 29/12015 (2013.01); G11C 2207/007 (2013.01);
Abstract

A method and apparatus for conducting at-speed testing of a memory array in an integrated circuit (IC) is disclosed. In one embodiment, an IC includes a memory array and a plurality of input circuits coupled to provide input signals into the memory array. Each of the plurality of input circuits includes an input flip-flop having a data output coupled to a corresponding input of the memory array, selection circuitry configured to select a data path to a data input of the input flip-flop and a data path shift register coupled to control a state of a selection signal provided to the selection circuitry, wherein the data path shift register includes a plurality of multiplexers. When operating the IC in a test mode, the plurality of input circuits is configured to provide input signals into the memory array at an operational clock speed of the IC.


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