The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2016

Filed:

Jan. 08, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;

Inventor:

DongHun Kwak, Suwon-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Suwon-Si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/14 (2006.01); G11C 16/08 (2006.01); G11C 16/34 (2006.01); G11C 7/14 (2006.01); G11C 7/22 (2006.01); G11C 16/16 (2006.01); G11C 16/26 (2006.01); H01L 27/115 (2006.01); G11C 16/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/14 (2013.01); G11C 7/14 (2013.01); G11C 7/227 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/16 (2013.01); G11C 16/26 (2013.01); G11C 16/349 (2013.01); G11C 16/3427 (2013.01); G11C 16/3445 (2013.01); H01L 27/115 (2013.01); G11C 16/10 (2013.01);
Abstract

A storage device is provided. The storage device includes a memory controller and at least one nonvolatile memory device including memory blocks having a pipe-shaped bit cost scalable (PBiCS) structure. Each of the memory blocks penetrates word lines stacked on a substrate in the form of plates and includes a first pillar, a second pillar, and a back-gate. The second pillar includes a semiconductor layer, an insulating layer, and a charge storage layer. The back-gate includes a pillar connection portion to connect the first and second pillars to each other and is disposed between the substrate and the word lines. The memory controller includes an adjacent cell management unit configured to control the at least one nonvolatile memory device such that a program operation, an erase operation or a read operation is performed on memory cells adjacent to the back-gate, unlike the other memory cells.


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