The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 26, 2016

Filed:

Dec. 22, 2014
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Mark T. Chan, San Jose, CA (US);

Shankar Prasad Sinha, San Jose, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01); G11C 11/419 (2006.01); H01L 27/11 (2006.01); G11C 11/40 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); H01L 27/1116 (2013.01); G11C 11/40 (2013.01);
Abstract

A memory cell includes a bistable element and two p-channel transistors (i.e., first and second p-channel transistors). The bistable element includes a plurality of inverting circuits and at least one data storage node. The bistable element may be formed in a first region on the substrate that is partially formed by a p-type diffusion region and an n-type diffusion region. The first and second p-channel transistors are coupled serially. The first p-channel transistor may also have its gate terminal coupled to the at least one data storage node of the bistable element. A method of manufacturing the memory cell includes forming a bistable element having at least first and second data storage nodes, forming a write-only port of the memory cell over an n-type diffusion region and forming a read-only port of the memory cell over a p-type diffusion region.


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