The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2016

Filed:

Sep. 14, 2011
Applicants:

Seok-bo Shim, Gyeonggi-do, KR;

Seok-cheol Yoon, Gyeonggi-do, KR;

Inventors:

Seok-Bo Shim, Gyeonggi-do, KR;

Seok-Cheol Yoon, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/00 (2006.01); H03L 7/081 (2006.01); G11C 5/02 (2006.01); G11C 5/06 (2006.01); G11C 29/02 (2006.01); H01L 25/065 (2006.01); H01L 21/66 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H03L 7/0816 (2013.01); G11C 5/025 (2013.01); G11C 5/063 (2013.01); G11C 29/023 (2013.01); G11C 29/025 (2013.01); G11C 29/028 (2013.01); H01L 22/32 (2013.01); H01L 24/06 (2013.01); H01L 25/0657 (2013.01); H01L 24/48 (2013.01); H01L 2224/05554 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/48227 (2013.01); H01L 2224/49175 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06565 (2013.01); H01L 2225/06596 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/3011 (2013.01);
Abstract

A semiconductor device includes a package substrate having a plurality of external connection terminals disposed on a first surface thereof and a plurality of internal connection terminals disposed on a second surface thereof and electrically connected with corresponding one of the external connection terminals, a first semiconductor chip stacked over the second surface of the package substrate and having a first flag pad for providing first information and a first internal circuit for adjusting a parameter by a first correction value in response to the first information provided from the first flag pad, and a second semiconductor chip stacked over the first semiconductor chip and having a second flag pad for providing second information and a second internal circuit for adjusting the parameter by a second correction value in response to the second information provided from the second flag pad.


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