The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2016
Filed:
Nov. 18, 2014
SK Hynix Inc., Gyeonggi-do, KR;
Sung-Soo Chi, Gyeonggi-do, KR;
SK Hynix Inc., Gyeonggi-do, KR;
Abstract
A latch circuit includes: first to Nth storage nodes where N is an even number equal to or more than four; and first to Nth pairs of transistors, each of which comprises a PMOS transistor and an NMOS transistor coupled in series with each other through a corresponding node among the first to Nth storage nodes. The PMOS transistor is coupled to one of the storage nodes included in previous one of the pairs of transistors at a gate of the PMOS transistor. The NMOS transistor is coupled to one of the storage nodes included in next one of the pairs of transistors at a gate of the NMOS transistor. The PMOS transistors of the first to Nth pairs of transistors are formed in a first active region. The NMOS transistors of the first to Nth pairs of transistors are formed in a second active region, separated from the first active region.