logo

For the Inventor, By the Inventor

The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9397282 B1

PDFFull Text
Date of Patent:
Jul. 19, 2016

Filed:

Feb. 12, 2015

Active matrix light emitting diode array and projector display comprising it

Applicants:

Chan-long Shieh, Paradise Valley, AZ (US);

Gang Yu, Santa Barbara, CA (US);

Inventors:

Chan-Long Shieh, Paradise Valley, AZ (US);

Gang Yu, Santa Barbara, CA (US);

Assignee:

CBRITE INC., Goleta, CA (US);

Attorneys:

Robert A. Parsons

Michael W. Goltry

Parsons & Goltry

Primary Examiner:

Evan Pert

Assistant Examiner:

Shaka White

Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 33/64 (2010.01); H01L 27/12 (2006.01); H01L 33/00 (2010.01); H01L 33/44 (2010.01); H01L 33/46 (2010.01); H01L 33/62 (2010.01); H01L 31/0368 (2006.01); H01L 27/146 (2006.01); H01L 31/0376 (2006.01); H01L 31/20 (2006.01);
U.S. Cl.
CPC ...
H01L 33/642 (2013.01); H01L 27/1225 (2013.01); H01L 27/1248 (2013.01); H01L 27/1262 (2013.01); H01L 27/1463 (2013.01); H01L 27/14663 (2013.01); H01L 27/14692 (2013.01); H01L 31/0368 (2013.01); H01L 31/0376 (2013.01); H01L 31/20 (2013.01); H01L 33/0075 (2013.01); H01L 33/44 (2013.01); H01L 33/46 (2013.01); H01L 33/62 (2013.01); H01L 2933/0025 (2013.01); H01L 2933/0033 (2013.01); H01L 2933/0066 (2013.01); H01L 2933/0075 (2013.01);
Abstract

A method of fabricating a pixelated projector display includes providing a wafer with a supporting substrate, a first semiconductive layer, an emission layer, and a second semiconductive layer. The wafer is patterned into an array of LEDs/LDs and a planarization layer is deposited over the array. One via for each LED/LD element is formed through the planarization layer. A MOTFT backplane is positioned on the planarization layer, one driver circuit in controlling electrical communication with each via through the planarization layer. A passivation layer is deposited over the MOTFT backplane and heat plugs are extended through the passivation layer, the MOTFT backplane, the planarization layer, and the III-V LED/LD wafer partially through the first semiconductive layer to thermally couple heat from the array of LEDs/LDs to the surface of the passivation layer. An upper end of the heat plugs is accessible for thermal coupling to a heat spreader and/or a heatsink.

Find Patent Forward Citations

Loading…