The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2016

Filed:

May. 03, 2012
Applicants:

Mehrdad M. Moslehi, Los Altos, CA (US);

David Xuan-qi Wang, Fremont, CA (US);

Sam Tone Tor, Pleasanton, CA (US);

Karl-josef Kramer, San Jose, CA (US);

Inventors:

Mehrdad M. Moslehi, Los Altos, CA (US);

David Xuan-Qi Wang, Fremont, CA (US);

Sam Tone Tor, Pleasanton, CA (US);

Karl-Josef Kramer, San Jose, CA (US);

Assignee:

Solexel, Inc., Milpitas, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01); H01L 31/18 (2006.01); H01L 21/67 (2006.01); H01L 21/683 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 31/18 (2013.01); H01L 21/67092 (2013.01); H01L 21/6835 (2013.01); H01L 21/6838 (2013.01); H01L 21/76259 (2013.01); H01L 2924/19042 (2013.01); Y10T 29/53683 (2015.01); Y10T 279/11 (2015.01);
Abstract

According to one embodiment, a releasing apparatus for separating a semiconductor substrate from a semiconductor template, the releasing apparatus having an enclosed pressure chamber having at least one gas inlet and at least one gas outlet. A top vacuum chuck for securing a released semiconductor substrate or semiconductor template in the enclosed pressure chamber. A bottom vacuum chuck for securing an attached semiconductor substrate and semiconductor template in the enclosed pressure chamber. A gap between the attached semiconductor substrate and semiconductor template and the top vacuum chuck allowing gas flowing through the gap to generate lifting forces on the attached semiconductor substrate and semiconductor template.


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