The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2016

Filed:

Apr. 02, 2015
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

John Z. Colt, Jr., Williston, VT (US);

John J. Ellis-Monaghan, Grand Isle, VT (US);

Leah M. Pastel, Essex Junction, VT (US);

Steven M. Shank, Jericho, VT (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/737 (2006.01); H01L 29/735 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01); H01L 29/73 (2006.01);
U.S. Cl.
CPC ...
H01L 29/737 (2013.01); H01L 29/0649 (2013.01); H01L 29/0821 (2013.01); H01L 29/1008 (2013.01); H01L 29/6625 (2013.01); H01L 29/66242 (2013.01); H01L 29/735 (2013.01); H01L 29/66265 (2013.01); H01L 29/7317 (2013.01);
Abstract

Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first terminal of the bipolar junction transistor is formed from a section of a device layer of a semiconductor-on-insulator wafer. An intrinsic base of the bipolar junction transistor is formed from an epitaxially-grown section of a first semiconductor layer, which is coextensive with a sidewall of the section of the device layer. A second terminal of the bipolar junction transistor is formed from a second semiconductor layer that is coextensive with the epitaxially-grown section of the first semiconductor layer. The epitaxially-grown section of a first semiconductor layer defines a first junction with the section of the device layer, and the second semiconductor layer defines a second junction with the epitaxially-grown section of the first semiconductor layer.


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