The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2016
Filed:
Oct. 06, 2011
Sung Kil Cho, Gyeonggi-do, KR;
Hai Won Kim, Gyeonggi-so, KR;
Sang Ho Woo, Gyeonggi-do, KR;
Seung Woo Shin, Gyeonggi-do, KR;
Gil Sun Jang, Gyeonggi-do, KR;
Wan Suk OH, Gyeonggi-do, KR;
Sung Kil Cho, Gyeonggi-do, KR;
Hai Won Kim, Gyeonggi-so, KR;
Sang Ho Woo, Gyeonggi-do, KR;
Seung Woo Shin, Gyeonggi-do, KR;
Gil Sun Jang, Gyeonggi-do, KR;
Wan Suk Oh, Gyeonggi-do, KR;
EUGENE TECHNOLOGY CO., LTD., Yongin-si, Gyeonggi-do, KR;
Abstract
Provided is a method of manufacturing a memory device having a 3-dimensional structure, which includes alternately stacking one or more dielectric layers and one or more sacrificial layers on a substrate, forming a through hole passing through the dielectric layers and the sacrificial layers, forming a pattern filling the through hole, forming an opening passing through the dielectric layers and the sacrificial layers, and supplying an etchant through the opening to remove the sacrificial layers. The stacking of the dielectric layers includes supplying the substrate with one or more gases selected from the group consisting of SiH, SiH, SiH, and SiH, to deposit a silicon oxide layer. The stacking of the sacrificial layers includes supplying the substrate with one or more gases selected from the group consisting of SiH, SiH, SiH, SiH, and dichloro silane (SiClH), and ammonia-based gas, to deposit a silicon nitride layer.