The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2016

Filed:

Jan. 29, 2015
Applicant:

SK Hynix Inc., Icheon-si Gyeonggi-do, KR;

Inventor:

Sang Kug Lym, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G06F 12/02 (2006.01); G11C 5/02 (2006.01); G11C 8/12 (2006.01); G11C 14/00 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 17/16 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G11C 5/06 (2013.01); G06F 12/0207 (2013.01); G11C 5/025 (2013.01); G11C 8/12 (2013.01); G11C 7/1084 (2013.01); G11C 7/22 (2013.01); G11C 14/0018 (2013.01); G11C 17/16 (2013.01); G11C 2029/4402 (2013.01);
Abstract

A semiconductor memory device may include a plurality of memory chips stacked upon one another, and electrically coupled to one another through a plurality of first TSVs. The semiconductor memory device may include a plurality of second memory chips stacked separately from the first memory chips, and the plurality of second memory chips electrically coupled to one another through a plurality of second TSVs. The semiconductor memory device may include a plurality of external connection electrodes coupled to both to the first memory chips and the second memory chips. Wherein one of the first and second memory chips may be accessed in response to chip select signals inputted through the external connection electrodes.


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