The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2016

Filed:

Apr. 19, 2013
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Sukalpa Biswas, Fremont, CA (US);

Wolfgang H. Klingauf, San Jose, CA (US);

Rong Zhang Hu, Saratoga, CA (US);

Shinye Shiu, Los Altos, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/08 (2016.01); G06F 12/12 (2016.01); G06F 1/32 (2006.01); G09G 5/395 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0871 (2013.01); G06F 1/3218 (2013.01); G06F 1/3275 (2013.01); G06F 12/0864 (2013.01); G06F 12/0893 (2013.01); G06F 12/122 (2013.01); G09G 5/395 (2013.01); G06F 2212/1028 (2013.01); G06F 2212/171 (2013.01); G06F 2212/6046 (2013.01); G09G 2330/021 (2013.01); G09G 2330/022 (2013.01); G09G 2360/121 (2013.01); Y02B 60/1225 (2013.01); Y02B 60/1228 (2013.01);
Abstract

Methods and systems for cache allocation schemes optimized for browsing applications. A memory controller includes a memory cache for reducing the number of requests that access off-chip memory. When an idle screen use case is detected, the frame buffer is allocated to the memory cache using a sequential allocation mode. Pixels are allocated to indexes of a given way in a sequential fashion, and then each way is accessed in a sequential fashion. When a given way is being accessed, the other ways of the memory cache are put into retention mode to reduce the leakage power.


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