The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 19, 2016

Filed:

Mar. 06, 2015
Applicant:

Arista Networks, Inc., Santa Clara, CA (US);

Inventors:

François Labonte, Santa Clara, CA (US);

Deepak Sebastian, San Francisco, CA (US);

Assignee:

Arista Networks, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); G06F 1/12 (2006.01); G06F 1/14 (2006.01);
U.S. Cl.
CPC ...
G06F 1/12 (2013.01); G06F 1/14 (2013.01);
Abstract

A method for distributing time information in network devices. The method includes sending a first clock signal from a first system control device (SCD) to a PLL chip, sending a first time of day (TOD) from the first SCD to a line card system control device (LC-SCD), sending a second clock signal from a second SCD to the PLL chip and sending a second TOD from the second SCD to the LC-SCD. The method further includes synchronizing a third clock signal, generated by the PLL chip, to the first clock signal, if the first SCD is operational. The method further includes sending the third clock signal to a network chip, deriving, using the third clock signal, a first network-chip-internal clock signal and applying the first network-chip-internal clock signal to increment a network-chip-internal TOD to obtain a third TOD. The method further includes synchronizing the third TOD to the first TOD.


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