The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 19, 2016
Filed:
Sep. 01, 2009
Pascal P Blais, Shefford, CA;
Paul F Fortier, Richelieu, CA;
Kang-wook Lee, Yorktown Heights, NY (US);
Jae-woong Nah, Closter, NJ (US);
Soojae Park, Wappingers Falls, NY (US);
Robert L Toutant, Sainte-Paul, CA;
Alain a Warren, Granby, CA;
Pascal P Blais, Shefford, CA;
Paul F Fortier, Richelieu, CA;
Kang-Wook Lee, Yorktown Heights, NY (US);
Jae-Woong Nah, Closter, NJ (US);
Soojae Park, Wappingers Falls, NY (US);
Robert L Toutant, Sainte-Paul, CA;
Alain A Warren, Granby, CA;
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Abstract
A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.