The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2016

Filed:

Dec. 14, 2015
Applicant:

Analog Devices Global, Hamilton, BM;

Inventors:

Colin G. Lyden, Baltimore, IE;

Pasquale Delizia, Newbury, GB;

Sanjay Rajasekhar, Newbury, GB;

Yogesh Jayarman Sharma, Santa Clara, CA (US);

Arthur J. Kalb, Santa Clara, CA (US);

Marvin L. Shu, Palo Alto, CA (US);

Gerard Mora-Puchalt, Catarroja, ES;

Roberto S. Maurino, Turin, IT;

Assignee:

Analog Devices Global, Hamilton, BM;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/38 (2006.01); H03M 1/00 (2006.01); H03M 1/06 (2006.01); H03M 1/12 (2006.01);
U.S. Cl.
CPC ...
H03M 1/002 (2013.01); H03M 1/0604 (2013.01); H03M 1/0626 (2013.01); H03M 1/1245 (2013.01); H03M 1/38 (2013.01);
Abstract

An input stage to an analog to digital converter (ADC) includes at least one sampling capacitor (SC) for sampling an input signal in acquire phases, a capacitive gain amplifier (CGA) for providing the input signal to the SC, and bandwidth control means. The bandwidth control means is configured to ensure that the SC has a first bandwidth during a first part of an acquire phase and has a second bandwidth during a subsequent, second, part of said acquire phase, the second bandwidth being smaller than the first. In this manner, first, the input signal is sampled at a higher, first, bandwidth allowing to take advantage of using a high-bandwidth CGA to minimize settling error on the SC, and, next, during a second part of the same acquire phase, the input signal is sampled at a lower, second, bandwidth advantageously decreasing noise resulting from the use of a high-bandwidth CGA.


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