The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2016

Filed:

Sep. 30, 2015
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Raghu Nandan Srinivasa, Bangalore, IN;

Tharun Nagulu, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/06 (2006.01); H03M 1/00 (2006.01); H03M 1/46 (2006.01); H03M 1/12 (2006.01); H03M 1/80 (2006.01);
U.S. Cl.
CPC ...
H03M 1/002 (2013.01); H03M 1/1245 (2013.01); H03M 1/464 (2013.01); H03M 1/466 (2013.01); H03M 1/00 (2013.01); H03M 1/12 (2013.01); H03M 1/804 (2013.01);
Abstract

The disclosure provides a successive approximation register analog to digital converter (SAR ADC). The SAR ADC includes a charge sharing DAC that includes an array of MSB (most significant bit) capacitors, an array of LSB (least significant bit) capacitors, and an error correction capacitor. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A successive approximation register (SAR) state machine is coupled to the zero crossing detector and operates the charge sharing DAC in a sampling mode and a conversion mode. During the sampling mode an input voltage is provided to the array of MSB capacitors and the error correction capacitor.


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