The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2016

Filed:

Dec. 12, 2013
Applicant:

Toyoda Gosei Co., Ltd., Kiyosu, JP;

Inventors:

Toru Oka, Kiyosu, JP;

Nariaki Tanaka, Kiyosu, JP;

Assignee:

Toyoda Gosei Co., Ltd., Kiyosu-shi, Aichi-ken, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/072 (2012.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 29/45 (2006.01); H01L 29/66 (2006.01); H01L 29/20 (2006.01); H01L 21/04 (2006.01); H01L 21/285 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41741 (2013.01); H01L 21/0485 (2013.01); H01L 21/28575 (2013.01); H01L 29/2003 (2013.01); H01L 29/45 (2013.01); H01L 29/452 (2013.01); H01L 29/66068 (2013.01); H01L 29/66727 (2013.01); H01L 29/66734 (2013.01); H01L 29/7802 (2013.01); H01L 29/7813 (2013.01); H01L 29/1608 (2013.01);
Abstract

A semiconductor device includes: a p-type semiconductor layer; an n-type semiconductor layer; a first electrode layer; a second electrode layer; and a control electrode layer. The first and second electrode layers are electrically connected such as to each operate at an identical potential. The first electrode layer is connected with a part of a surface of the second electrode layer which is opposite to a surface of the second electrode layer that is in contact with the p-type semiconductor layer. The second electrode layer is connected with a connection line which is a part of a peripheral line of a joint interface between the p-type semiconductor layer and the n-type semiconductor layer on an interface side between the second electrode layer and the p-type semiconductor layer, and is formed to be extended to a position on a control electrode layer side of the connection line.


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