The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2016

Filed:

Dec. 23, 2014
Applicant:

Imec Vzw, Leuven, BE;

Inventors:

Geert Hellings, Leuven, BE;

Dimitri Linten, Boortmeerbeek, BE;

Assignee:

IMEC VZW, Leuven, BE;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0255 (2013.01); H01L 27/0248 (2013.01); H01L 27/0886 (2013.01); H01L 29/0649 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract

An electrostatic discharge (ESD) protection device implemented in finFET technology is disclosed. The device has a reduced thickness shallow trench isolation (STI) layer which allows migration of high-doped drain implants therethrough to form regions extending under the STI layer thereby creating a planar-like region under the STI layer. Further, the regions are formed in an n-well layer provided between a substrate and the STI layer. The formation of the planar-like region under the STI layer has the advantage that part of the thermal energy produced in the device during an ESD event is generated under the STI layer where it can be more efficiently dissipated towards a substrate.


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