The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2016

Filed:

Jun. 28, 2012
Applicants:

Philip G. Emma, Danbury, CT (US);

Eren Kursun, Ossining, NY (US);

Jude A. Rivers, Cortlandt Manor, NY (US);

Inventors:

Philip G. Emma, Danbury, CT (US);

Eren Kursun, Ossining, NY (US);

Jude A. Rivers, Cortlandt Manor, NY (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 23/14 (2006.01); H05K 3/46 (2006.01); H01L 23/13 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2006.01); H01L 25/18 (2006.01); H05K 3/30 (2006.01); H01L 21/48 (2006.01);
U.S. Cl.
CPC ...
H01L 23/147 (2013.01); H01L 23/13 (2013.01); H01L 23/5382 (2013.01); H01L 23/5389 (2013.01); H01L 25/0652 (2013.01); H01L 25/18 (2013.01); H05K 3/465 (2013.01); H01L 21/4803 (2013.01); H01L 2225/06575 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/0002 (2013.01); H01L 2924/15311 (2013.01); H05K 3/30 (2013.01); Y10T 29/4913 (2015.01); Y10T 29/49128 (2015.01); Y10T 29/49137 (2015.01); Y10T 29/49146 (2015.01);
Abstract

A computer program product for generating and implementing a three-dimensional (3D) computer processing chip stack plan. The computer readable program code includes computer readable program code configured for receiving system requirements from a plurality of clients, identifying common processing structures and technologies from the system requirements, and assigning the common processing structures and technologies to at least one layer in the 3D computer processing chip stack plan. The computer readable program code is also configured for identifying uncommon processing structures and technologies from the system requirements and assigning the uncommon processing structures and technologies to a host layer in the 3D computer processing chip stack plan. The computer readable program code is further configured for determining placement and wiring of the uncommon structures on the host layer, storing placement information in the plan, and transmitting the plan to manufacturing equipment. The manufacturing equipment forms the 3D computer processing chip stack.


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