The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2016

Filed:

Oct. 17, 2014
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Woo-Kyung You, Suwon-si, KR;

Sang-Ho Rha, Seongnam-si, KR;

Jong-Min Baek, Suwon-si, KR;

Sang-Hoon Ahn, Goyang-si, KR;

Nae-In Lee, Seoul, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/3065 (2006.01); H01L 21/764 (2006.01);
U.S. Cl.
CPC ...
H01L 21/7682 (2013.01); H01L 21/3065 (2013.01); H01L 21/764 (2013.01); H01L 21/76826 (2013.01); H01L 21/76849 (2013.01); H01L 21/76877 (2013.01);
Abstract

Methods of forming a wiring structure are provided including forming an insulating interlayer on a substrate and forming a sacrificial layer on the insulating interlayer. The sacrificial layer is partially removed to define a plurality of openings. Wiring patterns are formed in the openings. The sacrificial layer is transformed into a modified sacrificial layer by a plasma treatment. The modified sacrificial layer is removed by a wet etching process. An insulation layer covering the wiring patterns is formed on the insulating interlayer. The insulation layer defines an air gap therein between neighboring wiring patterns.


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