The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2016

Filed:

Oct. 26, 2015
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Vinay Bhatsoori, Karnataka, IN;

George M. Braceras, Essex Junction, VT (US);

Venkatraghavan Bringivijayaraghavan, Tamilnadu, IN;

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01); G11C 7/06 (2006.01); H03K 3/037 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 7/065 (2013.01); G11C 7/106 (2013.01); G11C 7/1087 (2013.01); H03K 3/037 (2013.01);
Abstract

Multiplexed latches include a multiplexor having a first data input, a second data input, a selection input, and a multiplexor output. A first latch has a first latch clock input, and a first latch output. A second latch has a second latch clock input, and a second latch output. The first latch output is connected to the first data input of the multiplexor, and the second latch output is connected to the second data input of the multiplexor. A feedback loop connects the multiplexor output to the first latch clock input and the second latch clock input. When the selection signal is received by the multiplexor, the feedback loop feeds the output from the multiplexor back to the latches to maintain the existing latch output until the clock signal transitions, to avoid glitches in the multiplexor output when the selection signal and clock signal are not synchronized.


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