The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 12, 2016
Filed:
Jul. 06, 2012
Applicant:
Sumanth Jannyavula Venkata, Shakopee, MN (US);
Inventor:
Sumanth Jannyavula Venkata, Shakopee, MN (US);
Assignee:
SEAGATE TECHNOLOGY LLC, Cupertino, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/08 (2016.01); G06F 12/02 (2006.01); G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0873 (2013.01); G06F 3/061 (2013.01); G06F 3/068 (2013.01); G06F 3/0638 (2013.01); G06F 3/0641 (2013.01); G06F 12/0246 (2013.01); G06F 2212/205 (2013.01);
Abstract
A hybrid memory system includes a primary memory comprising a host memory space arranged as memory sectors corresponding to host logical block addresses (host LBAs). A secondary memory is implemented as a cache for the primary host memory. A hybrid controller is configured map the clusters of host LBAs to clusters of solid state drive (SSD) LBAs. The SSD LBAs correspond to a memory space of the cache. Mapping of the host LBA clusters to the SSD LBA clusters is fully associative such that any host LBA cluster can be mapped to any SSD LBA cluster.