Semiconductor memory device and system conducting parity check and operating method of semiconductor memory device

Abstract

A semiconductor memory device comprising of a parity check unit configured to receive a command signal and a parity signal to perform error checking in the command signal and output a parity indication signal; a delay unit including a plurality of registers configured to time delay by n clock cycles the parity indication signal and output a delayed parity indication signal; a command register configured to time delay by n clock cycles the command signal and output a delayed command; and a decoder configured to pass or block the delayed command signal based on the delayed parity indicator signal.