The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 12, 2016

Filed:

Nov. 09, 2015
Applicant:

Apple Inc., Cupertino, CA (US);

Inventors:

Greg M. Hess, Mountain View, CA (US);

James E. Burnette, II, San Jose, CA (US);

Assignee:

Apple Inc., Cupertino, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G06F 1/04 (2006.01); G01R 31/3185 (2006.01); G01R 31/317 (2006.01); H03M 1/08 (2006.01); H03M 1/20 (2006.01); H04L 1/20 (2006.01); G11B 20/10 (2006.01);
U.S. Cl.
CPC ...
G06F 1/04 (2013.01); G01R 31/31709 (2013.01); G01R 31/31858 (2013.01); G01R 31/318541 (2013.01); G01R 31/318552 (2013.01); G01R 31/318555 (2013.01); G01R 31/318594 (2013.01); H03M 1/0836 (2013.01); G11B 20/10398 (2013.01); H03M 1/205 (2013.01); H04L 1/205 (2013.01);
Abstract

Embodiments of a jitter detection circuit are disclosed that may allow for detecting both cycle and phase jitter in a clock distribution network. The jitter detection circuit may include a phase selector, a data generator, a delay chain, a logic circuit, and clocked storage elements. The phase selector may be operable to select a clock phase to be used for the launch clock, and the data generator may be operable to generate a data signal responsive to the launch clock. The delay chain may generate a plurality of outputs dependent upon the data signal, and the clocked storage elements may be operable to capture the plurality of outputs from the delay chain, which may be compared to expected data by the logic circuit.


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