The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 05, 2016

Filed:

Jan. 12, 2015
Applicant:

Fujitsu Limited, Kawasaki-shi, Kanagawa, JP;

Inventors:

Kazuya Arai, Kawasaki, JP;

Shinpei Ikegami, Kawasaki, JP;

Hitoshi Suzuki, Kawasaki, JP;

Kei Fukui, Kawasaki, JP;

Assignee:

FUJITSU LIMITED, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/18 (2006.01); H05K 3/46 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H05K 1/02 (2006.01); H05K 1/03 (2006.01); H01L 23/00 (2006.01); H05K 1/11 (2006.01); H05K 3/00 (2006.01);
U.S. Cl.
CPC ...
H05K 1/181 (2013.01); H01L 21/4857 (2013.01); H01L 23/49822 (2013.01); H05K 1/0298 (2013.01); H05K 1/0326 (2013.01); H05K 1/115 (2013.01); H05K 3/4682 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/01019 (2013.01); H01L 2924/01087 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/15311 (2013.01); H05K 1/113 (2013.01); H05K 3/0097 (2013.01); H05K 2201/10234 (2013.01); H05K 2203/0156 (2013.01); H05K 2203/1536 (2013.01); Y10T 29/4913 (2015.01); Y10T 29/49155 (2015.01); Y10T 29/49165 (2015.01);
Abstract

A method of manufacturing a circuit board includes forming a first electrode on a support substrate, covering the support substrate and the first electrode with a first insulating layer, polishing the first insulating layer to expose a first surface of the first electrode, forming a first wiring on the first insulating layer after exposing the first surface of the first electrode, the first wiring being connected to the first electrode, and removing the support substrate to expose a second surface of the first electrode after forming the first wiring.


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